1. Field of the Invention
The present invention relates generally to a semiconductor device employing a M (metal)-I (insulator)S (semiconductor) type FET (field-effect transistor), and more particularly to a semiconductor device used in a memory cell using a high-resistance element as a load in a static RAM (random-access memory).
2. Description of the Related Art
FIG. 5 shows a conventional so-called E/R (enhancement/resistance) type static RAM memory cell using a high-resistance element This memory comprises four transistors 1 to 4 and two constant-resistance resistors 5 and 6. These elements constitute a flip-flop.
Two problems must be considered in increasing the capacitance of a semiconductor memory device:
(1) Increase in standby current, and
(2) Instability in operation due to the increase in voltage drop caused by a load resistance.
In FIG. 5, if a node potential VM is set to a high level, e.g., a 5 V, a node potential VM' is set to a low level, e.g., about 0 V. In this case, the driver transistor 2 is turned on, and a leak current flows through a path constituted by a power source voltage Vcc, the high-resistance resistor 6 (the resistance is R), the driver transistor 2, and a ground voltage Vss. A standby current Isb of the static RAM is calculated by multiplying the leak current by the number of memory cells. Accordingly, the resistance R of the resistors 5 and 6 must satisfy the following condition: ##EQU1## (N: number of cell) For example, when Vcc=5 V, N=1 megabit (10.sup.6), and Isb is designed to 2 .mu. A or less, the following condition must be satisfied EQU R.gtoreq.2.5.times.10.sup.12 (.OMEGA.) (2)
The lower limit value in this condition is further raised in accordance with the degree of integration of the memory device. This is because the number of cells N is increased in accordance with the increase in capacitance of the memory device, while the value of the standby current Isb, which is required as a finished product, must be unchanged. Namely, this is the first problem, or the increase in standby current. In order to solve the first problem, there is a step of increasing the resistance value of the resistors 5 and 6. By increasing the resistance value, the standby current per cell (one flip-flop) is decreased in an adversely proportional manner. Thus, the standby current of the entire memory device can be limited to the value required by design specifications.
However, if the resistance values of resistors 5 and 6 are increased, the voltage drop is caused by the resistors accordingly. As a result, the node voltage V.sub.M lowers, and the operation of the driver transistors 1 and 2 become unstable. Namely, this is the second problem.
In order to solve the second problem, or the instability in operation due to the voltage drop, the following method has been proposed According to this method, the off-resistance r of driver transistor 1 and 2 is increased. If the off-resistance of the driver transistor 1 (in the OFF state) is r, the following equation can be established: ##EQU2##
In order to establish the relationship, V.sub.M .perspectiveto.Vcc, the relationship, r&gt;&gt;R, must be established
Normally, in order to obtain the value of V.sub.M, i.e. V.sub.M .gtoreq.0.99 Vcc, which is necessary for ensuring the stable operation of the memory device, the following relationship must be established:
On the other hand, the off-resistance r is give by the equation: EQU r.gtoreq.100.times.R (4)
by using a cut-off current Ic which is obtained when the gate voltage VG of the sub-threshold characteristic of the channel current shown in FIG. 6 is 0 V.
The cut-off current Ic is represented by; ##EQU3##
when the threshold value of the transistor (i.e. the gate voltage for causing a current of 1 .mu.A to flow) is set to VTH by using the so-called "sub-threshold slope" S (V/decade). The sub-threshold slope S (V/decade) is an inverse number of inclination of a straight portion S in FIG. 6, symbol V denotes a gate voltage, and "decade" is the number of digits of channels.
From formula (1) to (5), the following condition for V.sub.TH is given: EQU V.sub.TH .gtoreq.S log (50N) (6)
For example, in the case of a 1 M-bit static RAM (N=106), if a typical value of S, i.e., 0.1 (V/decade), is used, the following necessary condition is given: EQU V.sub.TH =0.77V (7)
Regarding this condition, the lower limit value is not lowered, rather, may be increased, in consideration of the fact that the value N increases in accordance with the increase in the degree of integration and capacitance, and that the value S does not change, irrespective of scaling rules. Accordingly, the value V.sub.TH of the static RAM increases, in the reverse direction to the direction of the scaling rule (or does hardly change). This tendency leads to an remarkable increase in concentration of channel region impurity (the thickness of a gate oxide film may be reduced in accordance with the degree of integration). The remarkable increase in concentration of channel region impurity intensifies the substrate bias effect of transfer gates 3 and 4 in the circuit shown in FIG. 5, since the transfer gates 3 and 4 are formed along with the transistors 1 and 2. In addition, the write-in in high level cannot be attained, degrading the characteristic of the cells. Furthermore, the amount of hot carriers is increased, and a reliable E/R type static RAM cannot be obtained.
From the above, it is understood that there are drawbacks in the method of solving the problem by increasing the off-resistance of driver transistors 1 and 2 and changing the threshold value.